1. Field of the Invention
This invention is directed to providing high resolution low cost digital phase detectors which can be used in digital phase locked loops (DPLLs) and shall also make possible other replacements of analog circuits by their digital implementations.
The high resolution phase detectors (HRPD) can be used for a wide range of data rates, and for wireless, optical, or wireline transmission and communication systems.
2. Background Art
Most of currently used digital phase detectors have resolution limited by a clock cycle time. While some most advanced digital phase detectors allow higher resolutions which are comparable with propagation delays of clock propagating gates, they have other limitations such as: complex algorithms which are conditioned by propagation delays of detector timing circuits, and dependency of their phase resolution on technological process and power supply variations.
The closest background solution is presented by Bogdan (U.S. Pat. No. 6,148,052). However this background solution requires additional oscillator circuit implemented with free running ring oscillator having unknown oscillation frequencies dependent on IC process deviations and power supply variations causing propagation delays deviations ranging from −50% to +50%.
Outputs of such additional unpredictable oscillator circuit are used to capture a phase of a first signal frame and a phase of a second signal frame, which need to be subtracted from each other to calculate a phase skew between the first signal frame and the second signal frame. Therefore in addition to the oscillator circuit, said background solution requires:                separate circuits for capturing first signal phase with oscillator outputs while other circuits are used for capturing second signal phase with the oscillator outputs;        additional circuits for subtracting such separately captured first signal phase from second signal phase;        oscillator calibration circuits for counting and capturing oscillator outputs over a predetermined fixed time period;        control unit circuits and subroutines for processing and using the above calibration results for recalculating the above mentioned inter-signal phase skews.        
There is a need for digital phase detectors which have simpler algorithms and greater independence versus the propagation delays of the detector timing circuits and the clock propagating gates.
Such much simpler digital phase detectors are provided by the present invention which eliminates the additional free running oscillator and the above mentioned additional circuits and calibration related subroutines. These improvements are achieved by changing principle of operation, as the present invention:
Propagates the first signal clock through serially connected gates and uses outputs of these gates for sensing phase of the second signal or propagates the second signal through serially connected gates and uses outputs of these gates for sensing phase of the first signal clock, instead of using outputs of the additional free running oscillator for capturing phases of the first signal and the second signal.
Since the first signal and the second signal are much more stable than the free running oscillator; the above calibration circuits are replaced by much simpler self-calibration means or by stabilizing propagation delays of the serially connected gates with phase locked loops or with delay locked loops.